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(R)
HI2570, CXD2570
E D FO R M ME N D SIGNS NEW DE
September 1997
O NOT REC
1-Bit AD/DA Converter For Audio Application
Features
* Two-Channel AD/DA Converters and Their Each Decimation and Oversampling Digital Filter in a Single Chip * Simplified External Parts with a Built-In Analog Circuit Around AD Converter * Distortion - ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.015% - DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.009% (-3dB) * S/N Ratio (Typical Values when FS = 16kHz) - ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80dB - DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90dB * Ripple in the Digital Filter Pass Band . . . . . . . 0.05dB< * Attenuation in the Digital Filter Rejection Band. . . 45dB>
Description
The HI2570, CXD2570 is a 1-bit stereo AD/DA converter which uses a 2nd-order system noise shaper. This LSI is especially suited for sampling frequency between 8kHz and 32kHz.
Function
* Data Can Be Input/Output at Rate of 1xFS with a BuiltIn Digital Filter * Multi-Channel Systems can be Connected Using Several HI2570, CXD2570Qs * The 32-Slot Serial Data Interface Enables Independent Selection of Data Frontward Truncation/Rearward Truncation and MSB First/LSB First * 512FS/1024FS (when FS = 8 to 16kHz) or 256FS/512FS/ 768FS/1024FS (When FS = 16 to 32kHz) Can be Used as the Master Clock * The Sampling Frequency of Not Only 8kHz or 16kHz, but 32kHz or 44.1kHz Can Be Used for Audio Equipment * Various Frequency Divided Clocks are Output for LSIs Connected
Applications
- Telephones, TV Conference Systems, Language Laboratory Equipment, TV Game Equipment and Electronic Musical Instrument
Ordering Information
PART NUMBER HI2570JCQ CXD2570Q TEMP. RANGE ( oC) -20 to 55 -20 to 55 PACKAGE 48 Ld MPQF 48 Ld MPQF PKG. NO. Q48.12x12-S Q48.12x12-S
Pinout
HI2570, CXD2570 (48 LEAD MQFP) TOP VIEW
AOUT1+ AVSS3 WO DASL1 DVDD DASL0 AIN1 AVDD1 AVSS1 SUB
AVDD3 AOUT1AVSS3 UCLK XCLK XVDD XTLI XTLO XVSS AVSS4 AOUT2AVDD4
1 2 3 4 5 6 7 8 9 10
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
NC NC
XSL2 XSL1 XSL0 MLSL MASL DVSS SOUT SIN BCK LRCK MS DVDD
26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24
AVSS4
AVSS2 AIN2
AVDD2
DVSS XMCK2
SUB NC
AOUT2+
TEST
CLR
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 1
File Number
4122.1
(R)
File Number 2
HI2570, CXD2570 Pin Descriptions
PIN NO. 1 2 3 4 AVDD3 AOUT1 (-) AVSS3 UCLK SYMBOL I/O -- O -- O DESCRIPTION Analog power supply for channel-1 DA converter Analog reversed phase output of channel-1 DA converter Analog GND for channel-1 DA converter Outputs a 1/2 frequency divider of clock input from oscillation pin XTLI (Pin 7). User clock output for the externally connected ICs. 256Fs/512Fs clock output. This provides the master clock for ICs operating in the slave mode when multiple CXD2570Qs are connected. Digital power supply for the master clock Crystal oscillation circuit input. Connects the crystal oscillator selected by the crystal selector pins XSL0 to 2 (Pins 34, 35 and 36). To input an external master clock, this pin is used. Crystal oscillation circuit output. Connects the crystal oscillator selected by the crystal selector pins XSL0 to 2 (Pins 34, 35 and 36). Digital GND for the master clock Analog GND for channel-2 DA converter Analog reversed phase output of channel-2 DA converter Analog power supply for channel-2 DA converter Analog forward phase output of channel-2 DA converter Analog GND for channel-2 DA converter Analog GND for channel-2 AD converter Analog input of channel-2 converter Analog power supply for channel-2 AD converter
5
XCLK
O
6 7
XVDD XTLI
-- I
8
XTLO
O
9 10 11 12 13 14 15 16 17 18 19
XVSS AVSS4 AOUT2 (-) AVDD4 AOUT2 (+) AVSS4 AVSS2 AIN1 AVDD2 NC SUB
-- -- O -- O -- -- I -- -- --
Connected to the substrate in the IC (having the same potential as power supply). Connect this pin to GND via a capacitor on the external printed wiring board.
20 21 22 23 24
NC DVSS XMCK2 TEST CLR
-- -- O I I Digital GND IC measurement. Normally, Low is output. Test. Normally, fixed at Low. Equipped with a pull-down resistor. System clear input. Normally, fixed at High; cleared at Low. Equipped with a pull-up resistor. Digital power supply. Master/slave mode switching input. High = Master mode. Low = Slave mode. Equipped with a pull-up resistor. Sampling frequency clock pin of serial I/O. Outputs in master mode (when Pin 26 is High). Inputs in slave mode (when Pin 26 is Low). Transfers channel-1 data at High; transfers channel-2 data at Low.
25 26
DVDD MS
-- I
27
LRCK
I/O
3
HI2570, CXD2570 Pin Descriptions
PIN NO. 28 BCK (Continued) I/O I/O DESCRIPTION Serial bit transfer clock for serial input data SIN or serial output data SOUT (64FS). Outputs in master mode (when Pin 26 is High). Inputs in slave mode (when Pin 26 is Low). Retrieves serial input data at ; send serial output data at . Serial data input of 2-channel sampling. The data format is 2's complement, and consists of 32-bit slot. Serial data output of 2-channel per sampling. The data format is 2's complement, and consists of 32-bit slot. Digital GND Selects whether 16-bit serial data is applied in the first 16-bits or the last 16bit of 32-bit slot in serial I/O. High = Frontward truncation; Low = Rearward truncation Selects whether 16-bit serial data is input/output at LSB first or MSB first in serial I/O. High = MSB first; Low = LSB first Crystal oscillator selection. Three bits, XSL0 to 2. Selects the clock frequency to be input from XTLI (Pin 7). Crystal oscillator selection. Three bits, XSL0 to 2. Selects the clock frequency to be input from XTLI (Pin 7). Crystal oscillator selection. Three bits, XSL0 to 2. Selects the clock frequency to be input from XTLI (Pin 7). IC measurement. Normally, fixed at High. IC measurement. Normally fixed at Low. Window masked when High; window open when Low (forced synchronization). Equipped with a pull-up resistor. Digital power supply
SYMBOL
29
SIN
I
30
SOUT
O
31 32
DVSS MASL
-- I
33 34
MLSL XSL0
I I
35
XSL1
I
36
XSL2
I
37 38 39
DASL0 DASL1 WO
I I I
40 41 42 43
DVDD NC NC SUB
-- -- -- --
Connected to the substrate in the IC (having the same potential as power supply). Connect this pin to GND via capacitor on the external printed wiring board. Analog power supply for channel-1 AD converter Analog input of channel-1 AD converter Analog GND for channel-1 AD converter Analog GND for channel-1 DA converter Analog forward phase output of channel-1 DA converter
44 45 46 47 48
AVDD1 AIN1 AVSS1 AVSS3 AOUT1 (+)
-- I -- -- O
4
HI2570, CXD2570
Absolute Maximum Ratings TA = 25oC
Supply Voltage (V DD). . . . . . . . . . . . . . . . . . . . . . VSS-0.5V to 7.0V Input Voltage (V 1). . . . . . . . . . . . . . . . . . .VSS - 0.5V to VDD + 0.5V Output Voltage (V 0) . . . . . . . . . . . . . . . . . VSS - 0.5V to VDD + 0.5V Operating Temperature (Topr) . . . . . . . . . . . . . . . . . . -20oC to 75C Storage Temperature (Tstg . . . . . . . . . . . . . . . . . . . -55oC to 150oC
I/O Capacitance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MIN .-- Input Pin (CIN) Output Pin (COUT) . . . . . . . . . . . . . . . . . . . -- Bidirectional Pin (CI/O) . . . . . . . . . . . . . . . . --- Measurement conditions: V DD = V1 = 0V, f = 1MHz TYP -- -- -- MAX 9pF 11pF 11 pF
Recommended Operating Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MIN Supply Voltage (Note 1) (VDD) 4.5V Ambient Temperature (TA) . . . . . . . . . . . . . . -20oC Sampling Frequency (Note 2) (FS). . . . . . . . 7kHz TYP 5.0V -- -- MAX 5.5V +75oC 33kHz
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. The analog power supplies for AD converters (Pins 17 and 44) must be turned on simultaneously with or before other poser supplies. turning on these power supplies after any other power supply may cause the device to fall into latch-up condition. this precaution, however, does not apply when turning off the power supplies. 2. Although the device can operate with FS frequencies such as FS = 44.1kHz or 48kHz, its analog characteristics deteriorate to extent. When used at only these FS frequencies, the CXD255Q is recommended that is pin-compatible with the CXD2570Q.
Electrical Specifications
TEST CONDITIONS PART NUMBER OR GRADE MIN TYP MAX UNITS APPLICABLE PINS
PARAMETER DC Characteristics Input Voltage
SYMBOL
AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 = XVSS = DVSS = 0V, TA = -20oC to 75oC VIHC VILC VIN Analog Input IOH = -2mA IOL = 4mA IOH = -4mA IOL = 4mA IOH = -12mA IOL = 16mA IOH = -2mA IOL = 4mA 0.7VDD O V SS VDD -0.5 0 VDD -0.5 0 VDD/2 0 VDD -0.8 0 -10 -40 -20 20 -40 VIN = VSS or VDD (Note 3) 250K -- -- O -- -- -- -- -- -- -- -- -- -- -- -50 50 -- 1M 43 -- 0.3VDD VDD VDD 0.4 VDD 0.4 VDD VDD/2 VDD 0.4 10 40 -12120 40 `2.5M 60 A A A A A mA *7 *8 *9 *10 *11 *12 V *6 V *5 V *4 V V *2 *3 V *1
Output Voltage
VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4
Input Leak Current 1 Input Leak Current 2 Input Leak Current 3 Input Leak Current 4 Output Leak Current Feedback Resistance Supply Current AC Characteristics SIN Setup Time SIN Hold Time LRCK Setup Time LRCK Hold Time LRCK Delay Time
ILI1 ILI2 ILI3 ILI4 ILZ RFB IDD
AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 = XVSS = DVSS = 0V, TA = -20oC to 75oC tsus ths tsul thl tdl Slave mode Slave mode Master mode CL = 130pF 10 15 10 15 -40 -- -- -- -- -- -- -- -- -- 30 ns ns ns ns ns
5
HI2570, CXD2570
Electrical Specifications
(Continued) PART NUMBER OR GRADE MIN 9 7 6 FS = 16kHz, 256Fs (XSL0 = XSL1 = XSL2 = Low 40 TYP -- -- -- -- MAX 65 42 40 200 UNITS ns ns ns ns
PARAMETER SOUT Delay Time SOUT Data Recovery Time SOUT Data Erase Time
SYMBOL tds tzd tdz
TEST CONDITIONS CL = 60pF
APPLICABLE PINS
XTLI Pulse Width for Low Period twl NOTES:
3. This includes current consumption at load resistance (RL = 3.9). Fs = 16kHz *1 All input pins except AIN1 and AIN2, and when bidirectional pins (BCK and LRCK) are input mode. *2 AIN1, AIN2 *3 XCLK, XMCK2, SOUT *4 AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-), UCLK *5 XTLO *6 When bidirectional pins (BCK and LRCK) are output mode *7 All input pins except AIN1 and AIN2 *8 When directional pins (BCK and LRCK) are input mode *9 MS, WO, CLR *10 TEST *11 SOUT, AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-), UCLK *12 Resistance between XTLO and XTLI
Analog Characteristics AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 =
XVSS = DVSS = 0V, TA = 25oC ITEM CONDITIONS MIN. TYP. MAX. UNIT
ADC + DAC Connection Overall Characteristics. Measured under the following conditions unless otherwise specified. Input waveform = 1kHz sine wave, 1.4Vrms (= 0dB), R IN = 16k XTAI = 16.384MHz (= 1024Fs, Fs = 16kHz) CLR = MS = WO = open (= 5V) SOUT and SIN directly coupled. S/N Ratio THD + N Dynamic Range Channel Separation Gain Difference Between Channels Gain Input Level RL = 3.9kW RIN = 0 RIN = 16 DC Offset (ADC Output) ADC Input Impedance 8kHz LPF 8kHz LPF 1kHz, -60dB 8kHz LPF 1kHz, 0dB 74 -- 74 -- -- -3 -- -- -- -- 80 0.015 80 97 0.1 0 0.1 1.4 030F 1.2 -- 0.03 -- -- -- +3 -- -- -- dB % dB dB dB dB Vrms Vrms Hex k
DAC characteristics in a single unit. Measured under the following conditions unless otherwise specified. Input data = 1kHz sine wave, full scale (= 0dB) XTAI = 16.384MHz (= 1024Fs, Fs = 16kHz CLR = WO = open (= 5V), MS = GND S/N Ratio THD + N Dynamic Range 8kHz LPF 8kHz LPF, -3dB 1kHz, -60dB 8kHz LPF 84 -- 82 90 0.009 88 -- 0.03 -- dB % dB
6
HI2570, CXD2570
Analog Characteristics AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 =
XVSS = DVSS = 0V, TA = 25oC (Continued) CONDITIONS 1kHz, 0dB ITEM Channel Separation Gain Difference Between Channels Output Level RL = 3.9kW MIN. -- -- 1.80 TYP. 100 0.05 1.93 MAX. -- -- 2.10 UNIT dB dB Vrms
Description of Functions
1. Serial data interface [Related pins] LRCK, BCK, SOUT, SIN, MASL, MLSL The serial data format is common for both SIN (DA converter input) and SOUT (AD converter output), consisting of two channels per sampling serial data represented by 2's complement. Each channel is divided into 32-bit slots, of which 16 bits are handled as data. MASL is used to select whether the 16 bits of valid data is placed in the first or the last half of the 32-bit slots. Similarly, MLSL is used to select whether the serial data is arranged at MSB first of LSB first.
MASL High Low Frontward truncation Rearward truncation MLSL High Low MSB first LSB first XSL2 L L L L XSL1 L L H H XSL0 L H L H CRYSTAL OSCILLATOR FREQUENCY 256Fs 512Fs 768Fs 1024Fs XCLK 256Fs 256Fs 256Fs 256Fs UCLK 128Fs 256Fs 384Fs 512Fs
*The CXD2555Q, which has the same pin configuration with this IC is recommended when using only Fs = 32kHz to 48kHz. 4. Crystal oscillator frequency selection (FS = 8kHz to 16kHz) [Related pins] XTLI, XTLO, XSL0, XSL1, XSL2, UCLK, XCLK With XSL2 fixed High, the device can be operated with lowFs frequencies. In this case, the frequency of the crystal oscillator can be selected by setting a combination of XSL0 and XSL1 accordingly.
CRYSTAL OSCILLATOR FREQUENCY* 512Fs -- 1024Fs --
2. Master mode/slave mode [Related pins] MS, LRCK, BCK When using the CXD2570Q in multiple units or in a pair with DA converter such as the CXD2558M, one of these CXD2570Qs should be in the master mode to serve as the source of clocks LRCK and BCK. The other ICs including CXD2570Qs are used in the slave mode, with their clocks LRCK and BCK supplied by the master CXD2570Q.
MS High Low MODE Master mode Slave mode LRCK AND BCK I/O Output Input
XSL2 H H H H
XSL1 L L H H
XSL0 L H L H
XCLK 512Fs -- 512Fs --
UCLK 256Fs -- 512Fs --
5. A/D converter input level Any desired input level VIN (m . 0.1Vrms) can be selected by adjusting RIN to generate the full-scale output of the AD converter. VIN generation of full-scale output varies with the products, and calculate the V IN maximum level (approximately -3dB below the full-scale) using the following equation to input the signal. (1) Fs = 16kHz to 48kHz (XSL2 = Low) RIN = 1230 VIN [Vrms] -1200 () (2) Fs = 8 to 16kHz (XSL2 = High) RIN = 26600 VIN [Vrms] -1200 () 6. D/A converter output level To change the D/A converter output level, adjust R15, R17, R30 and R32 in Application Circuit on page.
3. Crystal oscillator frequency selection (FS = 16kHz to 48kHz) [Related pins] XTLI, XTLO, XSL0, XSL1, XSL2, UCLK, XCLK By setting a combination of XSL0 and XSL1, with XSL2 fixed low, the frequency of the external crystal oscillator connected to XTLI and XTLO can be selected. In this case, XCLK outputs a clock whose frequency is always 256 times Fs, and UCLK outputs a clock that is half the crystal oscillator frequency. When supplying the master clock from some other external source, not a crystal oscillator, use XTLI for this clock input and leave XTLO open.
7
HI2570, CXD2570 Metric Plastic Quad Flatpack Packages (MQFP)
D D1
Q48.12x12-S
48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 B D D1 E E1 e L N e
SEATING PLANE 0.15 0.006 0.24 M B -C-
MILLIMETERS MIN 2.05 0.00 0.20 14.90 11.90 14.90 11.90 0.70 48 0.80 BSC MAX 2.55 0.30 0.45 15.70 12.40 15.70 12.40 1.10 NOTES 5 2 3, 4 2 3, 4 6 Rev. 0 2/96
MIN 0.081 0.000 0.008 0.587 0.469 0.587 0.469 0.028 48
MAX 0.100 0.011 0.017 0.618 0.488 0.618 0.488 0.043
E E1
PIN 1
0.032 BSC
-H-
A
NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane -C- . 3. Dimensions D1 and E1 to be determined at datum plane -H- . 4. Dimensions D1 and E1 do not include mold protrusion. 5. Dimension B does not include dambar protrusion. 6. "N" is the number of terminal positions.
A1 0o-10o
L 0.10/0.25 0.004/0.010
8

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